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301 |
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units - 2016 |
Abstract
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302 |
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016 |
Abstract
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303 |
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing - 2016 |
Abstract
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304 |
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems - 2016 |
Abstract
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305 |
A Mixed-Decimation MDF Architecturefor Radix-2k Parallel FFT - 2016 |
Abstract
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306 |
A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2016 |
Abstract
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307 |
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling - 2016 |
Abstract
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308 |
Code Compression for Embedded Systems Using Separated Dictionaries - 2016 |
Abstract
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309 |
A Dynamically Reconfigurable Multi-ASIP Architecture for Multi-standard and Multimode Turbo Decoding - 2016 |
Abstract
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310 |
Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order - 2016 |
Abstract
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311 |
Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators - 2016 |
Abstract
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312 |
A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones - 2016 |
Abstract
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313 |
Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication - 2016 |
Abstract
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314 |
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register - 2016 |
Abstract
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315 |
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis - 2016 |
Abstract
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316 |
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop - 2016 |
Abstract
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317 |
Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics - 2016 |
Abstract
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318 |
A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits - 2016 |
Abstract
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319 |
Multiple Constant Multiplication Algorithmfor High-Speed and Low-Power Design - 2016 |
Abstract
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320 |
A Low Power Reconfigurable LFSR - 2016 |
Abstract
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321 |
Low-Power Parallel Chien Search ArchitectureUsing a Two-Step Approach - 2016 |
Abstract
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322 |
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply - 2016 |
Abstract
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323 |
RF Power Gating: A Low-Power Technique for Adaptive Radios - 2016 |
Abstract
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324 |
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia - 2016 |
Abstract
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325 |
A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography - 2016 |
Abstract
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326 |
Low-Power FPGA Design Using Memorization-Based Approximate Computing - 2016 |
Abstract
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327 |
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation - 2016 |
Abstract
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328 |
Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs - 2016 |
Abstract
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329 |
Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches - 2016 |
Abstract
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|
330 |
Design of adder and subtractor circuits in majority logic-based field-coupled QCA Nano computing - 2016 |
Abstract
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331 |
Design of Efficient BCD Adders in Quantum Dot Cellular Automata - 2016 |
Abstract
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|
332 |
Energy dissipation of quantum-dot cellular automata logic gates - 2016 |
Abstract
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|
333 |
Design of area-delay efficient adder based circuits in quantum dot cellular automata - 2016 |
Abstract
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334 |
USE: A Universal, Scalable and Efficient clocking scheme for QCA - 2016 |
Abstract
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|
335 |
Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone Based Crossover - 2016 |
Abstract
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336 |
Design and simulation of Turbo encoder in quantum-dot cellular automata - 2016 |
Abstract
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337 |
Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016 |
Abstract
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338 |
A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits - 2016 |
Abstract
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|
339 |
Graph-Based Transistor Network GenerationMethod for Super gate Design - 2016 |
Abstract
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|
340 |
A Comparator-Based Rail Clamp - 2016 |
Abstract
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|
341 |
A Low Power Trainable Neuromorphic IntegratedCircuit That Is Tolerant to Device Mismatch - 2016 |
Abstract
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|
342 |
Analysis of 8 bit RCA adder at different nanometer regime - 2016 |
Abstract
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|
343 |
PNS-FCR: Flexible Charge RecyclingDynamic Circuit Technique forLow-Power Microprocessors - 2016 |
Abstract
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|
344 |
Design Methodology for Voltage-Scaled Clock Distribution Networks - 2016 |
Abstract
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345 |
One-Cycle Correction of Timing Errors in PipelinesWith Standard Clocked Elements - 2016 |
Abstract
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346 |
A Single-Ended With Dynamic Feedback Control 8T Sub threshold SRAM Cell - 2016 |
Abstract
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|
347 |
Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technologyfor Low-Voltage Operation - 2016 |
Abstract
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|
348 |
A Low-Power Incremental Delta–SigmaADC for CMOS Image Sensors - 2016 |
Abstract
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|
349 |
Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design - 2016 |
Abstract
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|
350 |
A 55-GHz-Bandwidth Track-and-Hold Amplifierin 28-nm Low-Power CMOS - 2016 |
Abstract
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|
351 |
Low-Power ASK Detector for Low ModulationIndexes and Rail-to-Rail Input Range - 2016 |
Abstract
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|
352 |
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design - 2016 |
Abstract
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|
353 |
A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System - 2016 |
Abstract
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|
354 |
An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016 |
Abstract
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|
355 |
An Improved Signed Digit Representation Approach for Constant Vector Multiplication - 2016 |
Abstract
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|
356 |
Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach - 2016 |
Abstract
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|
357 |
Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design - 2016 |
Abstract
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|
358 |
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs - 2016 |
Abstract
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|
359 |
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic - 2015 |
Abstract
|
|
360 |
A Modified Partial Product Generator for Redundant Binary Multipliers - 2016 |
Abstract
|
|
361 |
Design & Analysis of 16 bit RISC Processor Using low Power Pipelining - 2015 |
Abstract
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|
362 |
Design and Analysis of Approximate Compressors for Multiplication - 2015 |
Abstract
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|
363 |
Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics - 2015 |
Abstract
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|
364 |
Design and implementation of fast floating point multiplier unit - 2015 |
Abstract
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|
365 |
Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA - 2015 |
Abstract
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|
366 |
Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata - 2015 |
Abstract
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|
367 |
Design of area and power aware reduced Complexity Wallace Tree multiplier - 2015 |
Abstract
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|
368 |
Design of area and power efficient digital FIR filter using modified MAC unit - 2015 |
Abstract
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|
369 |
Design of low power and high speed Carry Select Adder using Brent Kung adder - 2015 |
Abstract
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|
370 |
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications - 2015 |
Abstract
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|
371 |
FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers - 2015 |
Abstract
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|
372 |
FPGA implementation of vedic floating point multiplier - 2015 |
Abstract
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|
373 |
FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier - 2015 |
Abstract
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|
374 |
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2015 |
Abstract
|
|
375 |
FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration - 2015 |
Abstract
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|
376 |
Intelligent and Adaptive Traffic Light Controller using FPGA - 2015 |
Abstract
|
|
377 |
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication - 2016 |
Abstract
|
|
378 |
Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications - 2015 |
Abstract
|
|
379 |
A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2015 |
Abstract
|
|
380 |
Analysis of ternary multiplier using booth encoding technique - 2015 |
Abstract
|
|
381 |
A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM - 2016 |
Abstract
|
|
382 |
HMFPCC - Hybrid-mode floating point conversion co-processor - 2015 |
Abstract
|
|
383 |
On the Analysis of Reversible Booth's Multiplier - 2015 |
Abstract
|
|
384 |
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding - 2016 |
Abstract
|
|
385 |
Reverse Converter Design via Parallel-Prefix Adders Novel Components, Methodology, and Implementations - 2015 |
Abstract
|
|
386 |
Revisiting Central Limit Theorem Accurate Gaussian Random Number Generation in VLSI - 2015 |
Abstract
|
|
387 |
Advanced low power RISC processor design using MIPS instruction set - 2015 |
Abstract
|
|
388 |
RTL implementation for AMBA ASB APB protocol at system on chip level - 2015 |
Abstract
|
|
389 |
Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications - 2015 |
Abstract
|
|
390 |
Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs - 2015 |
Abstract
|
|
391 |
Truncated ternary multipliers - 2015 |
Abstract
|
|
392 |
An_efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm - 2015 |
Abstract
|
|
393 |
A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT - 2015 |
Abstract
|
|
394 |
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016 |
Abstract
|
|
395 |
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC - 2015 |
Abstract
|
|
396 |
Obfuscating DSP Circuits via High-Level Transformations - 2015 |
Abstract
|
|
397 |
Obfuscating DSP Circuits via High-Level Transformations - 2015 |
Abstract
|
|
398 |
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing - 2015 |
Abstract
|
|
399 |
Data Encoding Techniques for Reducing EnergyConsumption in Network-on-Chip - 2015 |
Abstract
|
|
400 |
New Lightweight AES S-box Using LFSR - 2015 |
Abstract
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