PROJECT TITLE :

Design Methodology for Voltage-Scaled Clock Distribution Networks - 2016

ABSTRACT:

A low-voltage/swing clocking methodology is developed through each circuit and algorithmic innovations. The primary objective is to significantly scale back the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary parts: a completely unique D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the complete clock network and a unique clock tree synthesis algorithm to make sure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated at intervals an industrial style flow. Experimental results on ISCAS'eighty nine benchmark circuits demonstrate that the power consumed by the clock tree can be reduced by up to twenty seven% and 44% in, respectively, 32- and forty five-nm technologies while satisfying the identical timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same whereas achieving up to 32percent and fifteenpercent power savings in the overall flip-flop power of the benchmark circuits at, respectively, one- and one.5-GHz clock frequencies.