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1 |
Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis - 2018 |
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2 |
Fractional- Order Differentiators and Integrators with Reduced Circuit Complexity - 2018 |
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3 |
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop - 2018 |
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4 |
A High Performance Gated Voltage Level Translator with Integrated Multiplexer - 2018 |
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5 |
A Low-Power High-Speed Comparator for Precise Applications - 2018 |
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6 |
A Novel Five-input Multiple-function QCA Threshold Gate - 2018 |
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7 |
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) - 2018 |
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8 |
Binary To Gray Code Converter Implementation Using QCA - 2018 |
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9 |
MAES: Modified Advanced Encryption Standard for Resource Constraint Environments - 2018 |
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10 |
Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks - 2018 |
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11 |
Chip Design for Turbo Encoder Module for In-Vehicle System - 2018 |
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12 |
The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA - 2018 |
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13 |
Unbiased Rounding for HUB Floating-point Addition - 2018 |
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14 |
Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption - 2018 |
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15 |
FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications - 2018 |
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16 |
EEG Signal Denoising based on Wavelet Transform using Xilinx System Generator - 2018 |
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17 |
An Approach to LUT Based Multiplier for Short Word Length DSP Systems - 2018 |
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18 |
A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2018 |
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19 |
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters - 2018 |
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20 |
FIR Filter Design Based On FPGA - 2018 |
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21 |
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter - 2018 |
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22 |
Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences - 2018 |
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23 |
Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors - 2018 |
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24 |
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add - 2018 |
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25 |
Design and simulation of CRC encoder and decoder using VHDL - 2018 |
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26 |
Reconfigurable Decoder for LDPC and Polar Codes - 2018 |
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27 |
Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method - 2018 |
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28 |
An Efficient VLSI Architecture for Convolution Based DWT Using MAC - 2018 |
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29 |
Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields - 2018 |
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30 |
Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design - 2018 |
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31 |
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction - 2018 |
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32 |
Efficient Implementations of 4-Bit Burst Error Correction for Memories - 2018 |
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33 |
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits - 2018 |
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34 |
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications - 2018 |
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35 |
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation - 2018 |
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36 |
Logic BIST with Capture-per-Clock Hybrid Test Points - 2018 |
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37 |
Flexible Architecture of Memory BISTs - 2018 |
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38 |
Automotive Functional Safety Assurance by POST with Sequential Observation - 2018 |
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39 |
A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test - 2018 |
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40 |
VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors - 2018 |
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41 |
Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic - 2018 |
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42 |
An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators - 2018 |
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43 |
An Efficient FPGA Implementation of HEVC Intra Prediction - 2018 |
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44 |
Architecture Generator for Type-3 Unum Posit Adder/Subtractor - 2018 |
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45 |
Efficient Design for Fixed-Width Adder-Tree - 2018 |
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46 |
Research and implementation of hardware algorithms for multiplying binary numbers - 2018 |
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47 |
A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier - 2018 |
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48 |
Towards Efficient Modular Adders based on Reversible Circuits - 2018 |
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49 |
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder - 2018 |
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50 |
Reducing the Hardware Complexity of a Parallel Prefix Adder - 2018 |
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51 |
Power Efficient Approximate Booth Multiplier - 2018 |
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52 |
Optimizing Power-Accuracy trade-off in Approximate Adders - 2018 |
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53 |
On the Difficulty of Inserting Trojans in Reversible Computing Architectures - 2018 |
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54 |
Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system - 2018 |
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55 |
Low-Power Addition with Borrow-Save Adders under Threshold Voltage Variability - 2018 |
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56 |
Inexact Arithmetic Circuits for Energy Efficient loT Sensors Data Processing - 2018 |
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57 |
Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors - 2018 |
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58 |
Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits - 2018 |
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59 |
Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors - 2018 |
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60 |
Design, Evaluation and Application of Approximate High-Radix Dividers - 2018 |
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61 |
Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications - 2018 |
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62 |
Approximate Sum-of-Products Designs Based on Distributed Arithmetic - 2018 |
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63 |
A Cost-Effective Self-Healing Approach for Reliable Hardware Systems - 2018 |
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64 |
Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers - 2018 |
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65 |
Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design - 2018 |
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66 |
A Simple Yet Efficient Accuracy- Configurable Adder Design - 2018 |
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67 |
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing - 2018 |
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68 |
A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design - 2018 |
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69 |
A Low-Power Configurable Adder for Approximate Applications - 2018 |
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70 |
Approximate Quaternary Addition with the Fast Carry Chains of FPGAs - 2018 |
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71 |
A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads - 2018 |
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72 |
A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators - 2018 |
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73 |
A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS - 2018 |
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74 |
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation - 2018 |
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75 |
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates - 2018 |
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76 |
Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder - 2018 |
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77 |
Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique - 2018 |
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78 |
A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm - 2018 |
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79 |
Passive Noise Shaping in SAR ADC With Improved Efficiency - 2018 |
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80 |
Effect of Switched-Capacitor CMFB on the Gain of Fully Differential OpAmp for Design of Integrators - 2018 |
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81 |
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic - 2018 |
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82 |
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications - 2018 |
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83 |
Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique - 2018 |
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84 |
12T Memory Cell for Aerospace Applications in Nano scale CMOS Technology - 2017 |
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85 |
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit - 2017 |
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86 |
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata - 2017 |
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87 |
Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA - 2017 |
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88 |
Design of Efficient Programmable Test-per-Scan Logic BIST Modules - 2017 |
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89 |
Operating Frequency Improvement On FPGA Implementation Of A Pipeline Large-FFT Processor - 2017 |
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90 |
Clock-gating of streaming applications for energy efficient implementations on FPGAs - 2017 |
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91 |
Scenario-Aware Dynamic Power Reduction Using Bias Addition - 2017 |
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92 |
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique - 2017 |
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93 |
Multiplier less Unity-Gain SDF-FFTS - 2017 |
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94 |
A Scalable Approximate DCT Architectures For Efficient HEVC Compliant Video Coding - 2017 |
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95 |
Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities - 2017 |
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96 |
High Performance Integer DCT Architectures For HEVC - 2017 |
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97 |
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding - 2017 |
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98 |
Code Compression for Embedded Systems Using Separated Dictionaries - 2017 |
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99 |
Key Reconciliation Protocols for Error Correction of Silicon PUF Responses - 2017 |
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100 |
Two-Extra-Column Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes - 2017 |
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