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  4. Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction - 2018
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Category: MTech VLSI Projects
By MTech Projects
MTech Projects
11.Oct
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Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction - 2018

PROJECT TITLE :

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction - 2018

ABSTRACT:

The utilization of error-correction codes (ECCs) with advanced correction capability is a common system-level strategy to harden the memory against multiple bit upsets (MBUs). So, the development of ECCs with advanced error correction and low redundancy has become an necessary drawback, particularly for adjacent ECCs. Existing codes for mitigating MBUs mainly concentrate on the correction of up to 3-bit burst errors. As the technology scales and cell interval distance decrease, the number of affected bits will simply extend to a lot of than three bit. The previous strategies are thus not enough to satisfy the reliability demand of the applications in harsh environments. In this paper, a method to increase 3-bit burst error-correction (BEC) codes with quadruple adjacent error correction (QAEC) is presented. Initial, the look rules are specified and then a looking out algorithm is developed to find the codes that adjust to those rules. The H matrices of the three-bit BEC with QAEC obtained are presented. They don't need further parity check bits compared with a 3-bit BEC code. By applying the new algorithm to previous 3-bit BEC codes, the performance of 3-bit BEC is additionally remarkably improved. The encoding and decoding procedure of the proposed codes is illustrated with an example. Then, the encoders and decoders are implemented using a sixty five-nm library and therefore the results show that our codes have moderate total area and delay overhead to realize the correction ability extension.

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