|
501 |
Reverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations - 2014 |
Abstract
|
|
502 |
FPGA based partial reconfigurable fir filter design - 2014 |
Abstract
|
|
503 |
An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC - 2014 |
Abstract
|
|
504 |
An Efficient Field Programmable Gate ArrayImplementation of Double Precision Floating Point Multiplier using VHDL - 2014 |
Abstract
|
|
505 |
An Overview of Advance Microcontroller Bus Architecture Relate on AHB Bridge - 2014 |
Abstract
|
|
506 |
FPGA-Based Bit Error Rate PerformanceMeasurement of Wireless Systems - 2014 |
Abstract
|
|
507 |
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator |
Abstract
|
|
508 |
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip |
Abstract
|
|
509 |
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits |
Abstract
|
|
510 |
Fast Radix-10 Multiplication Using Redundant BCD Codes |
Abstract
|
|
511 |
A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values |
Abstract
|
|
512 |
Multifunction Residue Architectures for Cryptography |
Abstract
|
|
513 |
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay |
Abstract
|
|
514 |
32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler |
Abstract
|
|
515 |
Recursive Approach to the Design of a Parallel Self-Timed Adder |
Abstract
|
|
516 |
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications |
Abstract
|
|
517 |
Statistical Analysis of MUX-Based Physical Unclonable Functions |
Abstract
|
|
518 |
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme |
Abstract
|
|
519 |
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation |
Abstract
|
|
520 |
Efficient Integer DCT Architectures for HEVC |
Abstract
|
|
521 |
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm |
Abstract
|
|
522 |
A Method to Extend Orthogonal Latin Square Codes |
Abstract
|
|
523 |
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter |
Abstract
|
|
524 |
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator |
Abstract
|
|
525 |
On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays |
Abstract
|
|
526 |
Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata |
Abstract
|
|
527 |
Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding |
Abstract
|
|
528 |
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic |
Abstract
|
|
529 |
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes |
Abstract
|
|
530 |
Area–Delay–Power Efficient Carry-Select Adder |
Abstract
|
|
531 |
Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences |
Abstract
|
|
532 |
Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement |
Abstract
|
|
533 |
Digitally Controlled Pulse Width Modulator for On-Chip Power Management |
Abstract
|
|
534 |
Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States |
Abstract
|
|
535 |
Area-Delay Efficient Binary Adders in QCA |
Abstract
|
|
536 |
Sharing Logic for Built-In Generation of Functional Broadside Tests |
Abstract
|
|
537 |
Design and Estimation of delay, power and area for Parallel prefix adders |
Abstract
|
|
538 |
Detection of Hardware Trojan in SEA Using Path Delay |
Abstract
|
|
539 |
parallel multiplier accumulator Based on radix-2 Modified Booth Algorithm by using a VLSI architecture |
Abstract
|
|
540 |
Realization of 2:4 reversible decoder and its applications |
Abstract
|
|
541 |
All Optical Reversible Multiplexer Design using Mach-Zehnder interferometer |
Abstract
|
|
542 |
Design of Dedicated Reversible Quantum Circuitry for Square Computation |
Abstract
|
|
543 |
A Dynamically Reconfigurable Multi-ASIP Architecture for Multi standard and Multimode Turbo Decoding - 2015 |
Abstract
|
|
544 |
Energy Consumption of VLSI Decoders - 2015 |
Abstract
|
|
545 |
A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM - 2015 |
Abstract
|
|
546 |
Median Filter Architecture by Accumulative Parallel Counters - 2015 |
Abstract
|
|
547 |
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization - 2015 |
Abstract
|
|
548 |
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm² - 2015 |
Abstract
|
|
549 |
( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double Representation of Residues in [0,2] - 2015 |
Abstract
|
|
550 |
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols - 2015 |
Abstract
|
|
551 |
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication - 2015 |
Abstract
|
|
552 |
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits - 2015 |
Abstract
|
|
553 |
Ultralow-Energy Variation-Aware Design: Adder Architecture Study - 2015 |
Abstract
|
|
554 |
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits - 2015 |
Abstract
|
|
555 |
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing - 2015 |
Abstract
|
|
556 |
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator |
Abstract
|
|
557 |
Self-Immunity Technique to Improve Register File Integrity against Soft Errors |
Abstract
|
|
558 |
Design and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (2010) |
Abstract
|
|
559 |
Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (2010) |
Abstract
|
|
560 |
A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (2010) |
Abstract
|
|
561 |
Design and Implementation of Digital low power base band processor for RFID Tags (2010) |
Abstract
|
|
562 |
Design and Implementation of Reversible Watermarking for JPEG2000 Standard |
Abstract
|
|
563 |
FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging |
Abstract
|
|
564 |
Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (2010) |
Abstract
|
|
565 |
Design and Implementation of Lossless DWT/IDWT for Medical Images |
Abstract
|
|
566 |
High Performance Complex Number Multiplier Using Booth-Wallace Algorithm |
Abstract
|
|
567 |
High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming |
Abstract
|
|
568 |
Design of an Bus Bridge between OCP and AHB Protocol (2010) |
Abstract
|
|
569 |
Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter |
Abstract
|
|
570 |
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block |
Abstract
|
|
571 |
Design of Data Encryption Standard (DES) |
Abstract
|
|
572 |
Design of Distributed Arithmetic FIR Filter |
Abstract
|
|
573 |
Design of Universal Asynchronous Receiver Transmitter (UART) |
Abstract
|
|
574 |
Design of Triple Data Encryption Standard (DES) |
Abstract
|
|
575 |
Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm |
Abstract
|
|
576 |
Design of Dual Elevator Controller |
Abstract
|
|
577 |
Design of an ATM (Automated Teller Machine) Controller |
Abstract
|
|
578 |
Design of 8-Bit Pico Processor (VHDL) |
Abstract
|
|
579 |
Design of JPEG Image compression standard |
Abstract
|
|
580 |
Design of Digital FM Receiver using PLL (Phase Locked Loop) |
Abstract
|
|
581 |
Design of 16-bit QPSK (Quadrature Phase Shift Keying) |
Abstract
|
|
582 |
Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator |
Abstract
|
|
583 |
Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128- bits Key Length |
Abstract
|
|
584 |
Design of RS-232 System Controller |
Abstract
|
|
585 |
Design of CRC (Cyclic Redundancy Check) Generator (Verilog) |
Abstract
|
|
586 |
Design and Implementation of OFDM Transmitter (VHDL) |
Abstract
|
|
587 |
Design of 8-bit Microcontroller (VHDL) |
Abstract
|
|
588 |
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm |
Abstract
|
|
589 |
An Efficient Architecture for 3-D Discrete Wavelet Transform |
Abstract
|
|
590 |
The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation |
Abstract
|
|
591 |
Design of On-Chip Bus with OCP Interface |
Abstract
|
|
592 |
Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix. |
Abstract
|
|
593 |
Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms |
Abstract
|
|
594 |
An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform |
Abstract
|
|
595 |
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers |
Abstract
|
|
596 |
A Spurious-Power Suppression Technique for Multimedia/DSP Applications |
Abstract
|
|
597 |
Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length |
Abstract
|
|
598 |
DDR3 based lookup circuit for high-performance network processing |
Abstract
|
|
599 |
Multiplication Acceleration Through Twin Precision |
Abstract
|
|
600 |
32-bit RISC CPU Based on MIPS |
Abstract
|
