|
401 |
A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply - 2016 |
Abstract
|
|
402 |
A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications - 2016 |
Abstract
|
|
403 |
A Low-Complexity Multiple Error CorrectingArchitecture Using Novel Cross ParityCodes Over GF(2m). - 2015 |
Abstract
|
|
404 |
Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic - 2015 |
Abstract
|
|
405 |
Algorithm and Architecture for a Low-PowerContent-Addressable Memory Basedon Sparse Clustered Networks - 2015 |
Abstract
|
|
406 |
An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary CommonSub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis. - 2015 |
Abstract
|
|
407 |
Byte-Reconfigurable LDPC Codec DesignWith Application to High-Performance ECC ofNAND Flash Memory Systems - 2015 |
Abstract
|
|
408 |
Implementation of Sub-threshold AdiabaticLogic for Ultralow-Power Application - 2016 |
Abstract
|
|
409 |
A novel realization of reversible LFSR for its application in cryptography - 2015 |
Abstract
|
|
410 |
Preemptive Built-In Self-Test for In-Field Structural Testing - 2015 |
Abstract
|
|
411 |
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment - 2015 |
Abstract
|
|
412 |
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures - 2015 |
Abstract
|
|
413 |
Multiplexer based High Throughput S-box for AES Application - 2015 |
Abstract
|
|
414 |
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set - 2015 |
Abstract
|
|
415 |
A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults - 2015 |
Abstract
|
|
416 |
Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL - 2015 |
Abstract
|
|
417 |
Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications - 2015 |
Abstract
|
|
418 |
FPGA implementation of an advanced encoding and decoding architecture of polar codes - 2015 |
Abstract
|
|
419 |
Fault Tolerant Parallel Filters Based on Error Correction Codes - 2015 |
Abstract
|
|
420 |
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016 |
Abstract
|
|
421 |
A novel VHDL implementation of UART with single error correction and double error detection capability - 2015 |
Abstract
|
|
422 |
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) - 2015 |
Abstract
|
|
423 |
A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning - 2015 |
Abstract
|
|
424 |
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes - 2015 |
Abstract
|
|
425 |
VLSI Implementation of a Key Distribution Server Based Data Security Scheme for RFID System - 2015 |
Abstract
|
|
426 |
Optimized approach of sobel edge detection technique using Xilinx system generator - 2015 |
Abstract
|
|
427 |
PAQCS Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis - 2015 |
Abstract
|
|
428 |
Lossless and Reversible Data Hiding in Encrypted Images withPublic Key Cryptography - 2016 |
Abstract
|
|
429 |
Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication. - 2016 |
Abstract
|
|
430 |
Partially Parallel Encoder Architecturefor Long Polar Codes - 2015 |
Abstract
|
|
431 |
Quaternary Logic Lookup Table in Standard CMOS - 2015 |
Abstract
|
|
432 |
Secrecy Rate Optimizations for a MIMO Secrecy Channel With a Cooperative Jammer - 2015 |
Abstract
|
|
433 |
Fully Pipelined Low-Cost and High-Quality ColorDemosaicking VLSI Design for Real-Time VideoApplications. - 2015 |
Abstract
|
|
434 |
A Low-Power Architecture for the Designof a One-Dimensional Median Filter. - 2015 |
Abstract
|
|
435 |
Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder - 2015 |
Abstract
|
|
436 |
Optimized approach of sobel edge detection technique using Xilinx system generator - 2015 |
Abstract
|
|
437 |
Reconfigurable architecture of adaptive median filter — An FPGA based approach for impulse noise suppression - 2015 |
Abstract
|
|
438 |
High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis - 2015 |
Abstract
|
|
439 |
Glitch free combinational clock gating approach in nanometer VLSI circuits - 2015 |
Abstract
|
|
440 |
Low power compressor based MAC architecture for DSP applications - 2015 |
Abstract
|
|
441 |
Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing - 2015 |
Abstract
|
|
442 |
Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2015 |
Abstract
|
|
443 |
Power Optimization of Communication System Using Clock Gating Technique - 2015 |
Abstract
|
|
444 |
Low-Power Programmable PRPG With Test Compression Capabilities - 2015 |
Abstract
|
|
445 |
Design and synthesis of bandwidth efficient QPSK modulator for low power VLSI design - 2015 |
Abstract
|
|
446 |
A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015 |
Abstract
|
|
447 |
Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO - 2015 |
Abstract
|
|
448 |
TM-RF Aging-Aware Power-Efficient Register File Design for Modern Microprocessors - 2015 |
Abstract
|
|
449 |
Voltage mode implementation of highly accurate analog multiplier circuit - 2015 |
Abstract
|
|
450 |
Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015 |
Abstract
|
|
451 |
Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing - 2015 |
Abstract
|
|
452 |
Digtial to time converter using SET - 2015 |
Abstract
|
|
453 |
Design of high speed ternary full adder and threeinput XOR circuits using CNTFETs - 2015 |
Abstract
|
|
454 |
Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates - 2015 |
Abstract
|
|
455 |
Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2015 |
Abstract
|
|
456 |
Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell - 2015 |
Abstract
|
|
457 |
A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process - 2015 |
Abstract
|
|
458 |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist - 2015 |
Abstract
|
|
459 |
A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology - 2015 |
Abstract
|
|
460 |
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links - 2015 |
Abstract
|
|
461 |
A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015 |
Abstract
|
|
462 |
An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015 |
Abstract
|
|
463 |
Read Performance The Newest Barrier in Scaled STT-RAM - 2015 |
Abstract
|
|
464 |
On the Nonvolatile Performance of Flip-FlopSRAM Cells With a Single MTJ - 2015 |
Abstract
|
|
465 |
High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors - 2015 |
Abstract
|
|
466 |
High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis - 2015 |
Abstract
|
|
467 |
Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model - 2015 |
Abstract
|
|
468 |
A CMOS PWM Transceiver Using Self-Referenced Edge Detection - 2015 |
Abstract
|
|
469 |
Area Delay Power Efficient Carry Select Adder - 2014 |
Abstract
|
|
470 |
On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays - 2014 |
Abstract
|
|
471 |
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code - 2014 |
Abstract
|
|
472 |
A Method to Extend Orthogonal Latin Square Codes - 2014 |
Abstract
|
|
473 |
Design and Estimation of delay power and area for Parallel prefix adders - 2014 |
Abstract
|
|
474 |
Design and FPGA implementation of compressor based Vedic multiplier - 2014 |
Abstract
|
|
475 |
A Combined SDC SDF Architecture for Normal I/O Pipelined Radix-2 FFT - 2015 |
Abstract
|
|
476 |
Area Delay Efficient Binary Adders in QCA - 2014 |
Abstract
|
|
477 |
Test Versus Security Past and Present - 2014 |
Abstract
|
|
478 |
Skewed Load Test Cubes Based on Functional Broadside Tests for a Low Power Test Set - 2014 |
Abstract
|
|
479 |
High Speed Convolution and De convolution Algorithm - 2014 |
Abstract
|
|
480 |
Fast Radix 10 Multiplication Using Redundant BCD Codes - 2014 |
Abstract
|
|
481 |
Low Complexity Low Latency Architecture for Matching of Data Encoded With Hard Systematic Error Correcting Codes - 2014 |
Abstract
|
|
482 |
Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing - 2014 |
Abstract
|
|
483 |
Design of High Performance 64 bit MAC Unit - 2014 |
Abstract
|
|
484 |
Thwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison - 2014 |
Abstract
|
|
485 |
Low Power Test Generation by Merging of Functional Broadside Test Cubes - 2014 |
Abstract
|
|
486 |
Design of Dedicated Reversible Quantum Circuitry for Square Computation - 2014 |
Abstract
|
|
487 |
A Look Ahead Clock Gating Based on Auto Gated Flip Flops - 2014 |
Abstract
|
|
488 |
A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) - 2014 |
Abstract
|
|
489 |
Aging Aware Reliable Multiplier Design With Adaptive Hold Logic - 2014 |
Abstract
|
|
490 |
An Accuracy Adjustment Fixed Width Booth Multiplier Based on Multilevel Conditional Probability - 2014 |
Abstract
|
|
491 |
Arithmetic Based Binary to RNS Converter Modulo {2n ± k} for jn-Bit Dynamic Range - 2014 |
Abstract
|
|
492 |
Critical Path Analysis and Low Complexity Implementation of the LMS Adaptive Algorithm - 2014 |
Abstract
|
|
493 |
Design Flow for Flip Flop Grouping in Data Driven Clock Gating - 2014 |
Abstract
|
|
494 |
Design of Efficient Binary Comparators in Quantum Dot Cellular Automata - 2014 |
Abstract
|
|
495 |
Efficient Hardware Implementation of Encoder and Decoder for Golay Code - 2014 |
Abstract
|
|
496 |
Efficient Integer DCT Architectures for HEVC - 2014 |
Abstract
|
|
497 |
Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} - 2014 |
Abstract
|
|
498 |
Fault Tolerant Parallel Filters Based on Error Correction Codes - 2014 |
Abstract
|
|
499 |
Low Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure - 2014 |
Abstract
|
|
500 |
On the Design of Efficient Modulo 2n+1 Multiply Add Add Units - 2014 |
Abstract
|
