PROJECT TITLE:

Multiplexer based High Throughput S-box for AES Application - 2015

ABSTRACT:

In this project a multiplexer based S-box architecture with five stage pipelining is proposed The proposed AES S-box were implemented on Xilinx device XC5VLX20T Virtex-5 FPGA. The results are compared with modular style design. This implementation offers ten.55 ns path delay with the slice area of 52 while not pipelining and 1.74 ns path delay with the slice area of thirty six by introducing five stage pipelining. The results show that the pipelined changed structure reduces the important path therefore the through put is increased to four.5Gbps.