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101 |
Two Approximate Voting Schemes for Reliable Computing - 2017 |
Abstract
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102 |
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder - 2017 |
Abstract
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103 |
Towards Low Power Approximate DCT Architecture for HEVC Standard - 2017 |
Abstract
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104 |
LLR-based Successive-Cancellation List Decoder for Polar Codes with Multi-bit Decision - 2017 |
Abstract
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105 |
SPARX - A Side-Channel Protected Processor for ARX-based Cryptography - 2017 |
Abstract
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106 |
Novel Solutions of Delta-Sigma Based Rectifying Encoder - 2017 |
Abstract
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107 |
Probabilistic Error Modeling for Approximate Adders - 2017 |
Abstract
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108 |
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping - 2017 |
Abstract
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109 |
Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices - 2017 |
Abstract
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110 |
Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity Sharing - 2017 |
Abstract
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111 |
Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications - 2017 |
Abstract
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112 |
Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-like Block Ciphers - 2017 |
Abstract
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113 |
Efficient Soft Cancelation Decoder Architectures for Polar Codes - 2017 |
Abstract
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114 |
An Efficient O(N) Comparison-Free Sorting Algorithm - 2017 |
Abstract
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115 |
A novel method of decoding the BCH code based on norm syndrome to improve the error correction efficiency - 2017 |
Abstract
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116 |
A Custom Accelerator for Homomorphic Encryption Applications - 2017 |
Abstract
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117 |
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator - 2017 |
Abstract
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118 |
Overloaded CDMA Crossbar for Network-On-Chip - 2017 |
Abstract
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119 |
LFSR-Based Generation of Multi cycle Tests - 2017 |
Abstract
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120 |
An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA - 2017 |
Abstract
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121 |
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations - 2017 |
Abstract
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122 |
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares - 2017 |
Abstract
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123 |
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits - 2017 |
Abstract
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124 |
Software Implementation of the Recursive Discrete Fourier Transform - 2017 |
Abstract
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125 |
Design of Efficient Multiplier less Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation - 2017 |
Abstract
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126 |
A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC - 2017 |
Abstract
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127 |
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters - 2017 |
Abstract
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128 |
Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic - 2017 |
Abstract
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129 |
Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM - 2017 |
Abstract
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130 |
Design and Applications of Approximate Circuits by Gate-Level Pruning - 2017 |
Abstract
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131 |
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities - 2017 |
Abstract
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132 |
Efficient RNS Scalers for the Extended Three-Moduli Set(2n -1; 2n+p; 2n + 1) - 2017 |
Abstract
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133 |
Area-time Efficient Architecture of FFT-based Montgomery Multiplication - 2017 |
Abstract
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134 |
Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition - 2017 |
Abstract
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135 |
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA - 2017 |
Abstract
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136 |
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA - 2017 |
Abstract
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137 |
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division - 2017 |
Abstract
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138 |
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials - 2017 |
Abstract
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139 |
A Structured Visual approach to GALS Modelling and Verification of Communication Circuits - 2017 |
Abstract
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140 |
Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm - 2017 |
Abstract
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141 |
Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression - 2017 |
Abstract
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142 |
Powering Wearable Sensors with a Low-Power CMOS Piezoelectric Energy Harvesting Circuit - 2017 |
Abstract
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143 |
Low Power 8-bit ALU Design Using Full Adder and Multiplexer - 2017 |
Abstract
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144 |
Evolutionary Approach to Approximate Digital Circuits Design - 2017 |
Abstract
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145 |
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology - 2017 |
Abstract
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146 |
Design And Analysis Of Combinational Coding Circuits Using Adiabatic Logic - 2017 |
Abstract
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147 |
Analysis and Design of the Classical CMOS Schmitt Trigger in Sub threshold Operation - 2017 |
Abstract
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148 |
A Single-ended with Dynamic Feedback Control 8T Sub threshold SRAM Cell - 2017 |
Abstract
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149 |
A Low Power, Low Noise Amplifier For Recording Neural Signals amplification in SCL 180nm - 2017 |
Abstract
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150 |
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply - 2017 |
Abstract
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151 |
A band-selective low-noise amplifier using an improved tunable active inductor for 3–5 GHz UWB receivers - 2017 |
Abstract
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152 |
Fault Tolerant Logic Cell FPGA - 2017 |
Abstract
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153 |
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage - 2017 |
Abstract
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154 |
Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design - 2017 |
Abstract
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155 |
Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template - 2017 |
Abstract
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156 |
Register – Less NULL Conventional Logic - 2017 |
Abstract
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157 |
Probability-Driven Multibit Flip-Flop Integration With Clock Gating - 2017 |
Abstract
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158 |
Optimized Memristor-Based Multipliers - 2017 |
Abstract
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159 |
Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits - 2017 |
Abstract
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160 |
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops - 2017 |
Abstract
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161 |
High-performance engineered gate transistor-based compact digital circuits - 2017 |
Abstract
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162 |
High Performance Ternary Adder using CNTFET - 2017 |
Abstract
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163 |
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology - 2017 |
Abstract
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164 |
Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders - 2017 |
Abstract
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165 |
Design and Low Power Magnitude Comparator - 2017 |
Abstract
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166 |
Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays - 2017 |
Abstract
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|
167 |
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications - 2017 |
Abstract
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|
168 |
A Memristor Based Binary Multiplier - 2017 |
Abstract
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169 |
A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies - 2017 |
Abstract
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|
170 |
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar - 2017 |
Abstract
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|
171 |
Delay Analysis for Current Mode Threshold Logic Gate Designs - 2017 |
Abstract
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172 |
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications - 2017 |
Abstract
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|
173 |
A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier - 2017 |
Abstract
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|
174 |
Binary Adder Circuit Design Using Emerging MIGFET Devices - 2017 |
Abstract
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|
175 |
CMCS: Current-Mode Clock Synthesis - 2017 |
Abstract
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|
176 |
A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA - 2017 |
Abstract
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|
177 |
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression - 2017 |
Abstract
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|
178 |
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017 |
Abstract
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|
179 |
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding - 2017 |
Abstract
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|
180 |
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices - 2017 |
Abstract
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|
181 |
A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes - 2017 |
Abstract
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|
182 |
On the VLSI Energy Complexityof LDPC Decoder Circuits - 2017 |
Abstract
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|
183 |
Efficient Designs of Multi ported Memory on FPGA - 2017 |
Abstract
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|
184 |
Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields - 2017 |
Abstract
|
|
185 |
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs - 2017 |
Abstract
|
|
186 |
Reconfigurable Constant Multiplication for FPGAs - 2017 |
Abstract
|
|
187 |
DLAU: A Scalable Deep Learning Accelerator Uniton FPGA - 2017 |
Abstract
|
|
188 |
Area-Efficient Architecture for Dual-Mode DoublePrecision Floating Point Division - 2017 |
Abstract
|
|
189 |
A Novel Data Format for Approximate Arithmetic Computing - 2017 |
Abstract
|
|
190 |
A Structured Visual approach to GALS Modellingand Verification of Communication Circuits - 2017 |
Abstract
|
|
191 |
Realization of a hardware generator for the Sum of Absolute Difference component - 2017 |
Abstract
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|
192 |
Optimization of Constant Matrix Multiplication with Low Power and High Throughput - 2017 |
Abstract
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|
193 |
An Optimised 3x3 Shift and Add Multiplier on FPGA - 2017 |
Abstract
|
|
194 |
Comparative study of 16-order FIR filter design using different multiplication techniques - 2017 |
Abstract
|
|
195 |
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing - 2017 |
Abstract
|
|
196 |
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder - 2017 |
Abstract
|
|
197 |
Probabilistic Error Analysis of Approximate Recursive Multipliers - 2017 |
Abstract
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|
198 |
Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor - 2017 |
Abstract
|
|
199 |
On the Implementation of Computation-in-Memory Parallel Adder - 2017 |
Abstract
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|
200 |
Multi-operand logarithmic addition/subtraction based on Fractional Normalization - 2017 |
Abstract
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