JA Purity IV
  • HOME
    • Business
    • Corporate
    • Logistics
    • Product
    • News / Magazine
  • MTECH PROJECTS
    • COMPUTER SCIENCE
      • MTech Python Projects
        • Machine Learning Projects
        • Deep Learning Projects
        • Blockchain Projects
        • django Projects
      • MTech Java Projects
        • Cloud Computing Projects
        • Data Mining Projects
        • Mobile Computing Projects
        • Networking Projects
      • MTech NS2 Projects
        • Wireless Communication Projects
        • Vehicular Technology Projects
      • MTech Hadoop Projects
      • MTech Android Projects
    • ELECTRONICS
      • MTech DSP Projects
      • MTech DIP Projects
      • MTech VLSI Projects
      • MTech Communication Projects
    • ELECTRICAL
      • MTech Power Systems Projects
      • MTech Power Electronics Projects
      • MTech Control Systems Projects
    • OTHER
      • Chemical Projects
      • Mechanical Projects
      • All Other Projects
  • EMBEDDED KITS
    • MTech Embedded Kits
    • BTech Embedded Kits
  • PROJECTS+
  • PUBLISHING
    • Research Publishing
    • Authors Guidelines
    • Publishing Policy
  • CONTACT US

Contact Us

  • 4517 Washington Ave. Manchester, Kentucky 39495
  • (201) 555-0124
  • hello@purityiv.com

Welcome to MTech Projects - Online Projects for MTech Students

  • My Account
  • Careers
  • Downloads
  • Blog
JA Purity IV
  • Email Us
  • Phone Number
  • Open Hours
  • HOME
    • Business
    • Corporate
    • Logistics
    • Product
    • News / Magazine
  • MTECH PROJECTS

    MTech Python Projects

    • Machine Learning Projects
    • Deep Learning Projects
    • Blockchain Projects
    • django Projects

    MTECH JAVA PROJECTS

    • Cloud Computing Projects
    • Data Mining Projects
    • Mobile Computing Projects
    • Networking Projects

    MTECH NS2 PROJECTS

    • Wireless Communication Projects
    • Vehicular Technology Projects
    • MTech Hadoop Projects
    • MTech Android Projects

    ELECTRONICS

    • MTech DSP Projects
    • MTech DIP Projects
    • MTech VLSI Projects
    • MTech Communication Projects

    ELECTRICAL

    • MTech Power Systems Projects
    • MTech Power Electronics Projects
    • MTech Control Systems Projects

    OTHER

    • Chemical Projects
    • Mechanical Projects
    • All Other Projects
  • EMBEDDED KITS
    • MTech Embedded Kits
    • BTech Embedded Kits
  • PROJECTS+
  • PUBLISHING
    • Research Publishing
    • Authors Guidelines
    • Publishing Policy
  • CONTACT US

Project Enquiry

  1. You are here:  
  2. Home
  3. MTech VLSI Projects
  4. Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters - 2017
Details
Category: MTech VLSI Projects
By MTech Projects
MTech Projects
11.Oct
Hits: 1

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters - 2017

PROJECT TITLE :

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters - 2017

ABSTRACT:

Reconfigurable finite-impulse response (FIR) filters are one in every of the most widely implemented elements in Internet of Things systems that need flexibility to support many target applications while consuming the minimum amount of power to suits the strict design requirements of portable devices. Because of the numerous power consumption in the multiplier components of the FIR filter, various techniques aimed at reducing the switching activity of these multipliers have been proposed in the literature. However, these techniques rarely exploit the flexibleness on the algorithmic level, which can lead to extra benefits. In this paper, FIR filter multipliers are extensively characterized with power simulations, providing a strategy for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique will not require any hardware overhead and it permits the possibility of scaling the facility consumption of the filter at runtime, while making certain the full baseline performance of any programmed filter whenever it is needed. The analyzed FIR filters were fabricated in an exceedingly 28nm FD-SOI test chip and measured at a near-threshold, 600mV provide voltage. For example, by rigorously choosing slightly perturbed coefficients in a very low-pass configuration, power savings of up to thirty threepercent are achieved when accepting a 3dB degradation on the stopband, as compared with the baseline implementation of the filter.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

Previous article: A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC - 2017 A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC - 2017 Next article: Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic - 2017 Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic - 2017
COMPUTER SCIENCE PROJECTS ELECTRONICS PROJECTS MTech DSP Projects MTech DIP Projects MTech VLSI Projects MTech VHDL Projects MTech Verilog Projects MTech Communication Projects ELECTRICAL PROJECTS EMBEDDED PROJECTS MECHANICAL PROJECTS

sell academic m.tech, btech and be projects online

sell academic m.tech, btech and be projects online

Academic Final Year Projects

QUICK LINKS

  • Python Projects
  • Java Projects
  • Android Projects
  • Digital Signal Processing
  • Image Processing Projects
  • VLSI Projects
  • Power Systems
  • Power Electronics
SUPPORT
+91 9573777164
9:00am - 6:00pm IST
info@mtechprojects.com

Navigate

  • ABOUT
  • TESTIMONIALS
  • FIND A DEALER
  • CAREERS

CONTACT

  • CONTACT
  • FAQ
  • RESOURCES
  • EMAIL US

Useful links

  • REFUND & RETURN POLICY
  • PRIVACY POLICIES

Support

  • FACEBOOK
  • TWITTER
  • PINTEREST
  • GOOGLE PLUS
Copyright © 2026 MTech Projects. All Rights Reserved.