PROJECT TITLE :

Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic - 2017

ABSTRACT:

This paper presents a new architecture for distributed arithmetic (DA) based Least Mean Sq. (LMS) adaptive filter with low hardware complexity and important path. It's well-known that for DA based adaptive filter, the throughput depends on essential path and range of clock cycles to provide the output. In the proposed technique, we maintained the same number of clock cycles using multiplexed look-up tables (LUTs) that reduces the hardware complexity and essential path compared to best existing scheme. For instance, the hardware complexity will be lowered down by a.N, whereas the important path can be reduced by TA + TM, with a, N, TA and TM being the number of reduced hardware components, range of filter taps, adder and multiplexer computational delays, respectively. Synthesis result shows that for almost similar space and power performance, the proposed theme achieves a gain of twenty seven.sixp.c thanks to clock speedup which leads to additional throughput and power will be lowered compared to best existing scheme.