PROJECT TITLE :

Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities - 2017

ABSTRACT:

This paper presents a framework based on the logarithmic variety system to implement adaptive filters with error nonlinearities in hardware. The framework is demonstrated through pipelined implementations of 2 recently proposed adaptive filtering algorithms primarily based on logarithmic value, namely, least mean logarithmic square (LMLS) and least logarithmic absolute distinction (LLAD). To the simplest of our knowledge, the proposed architectures are the first attempts to implement each LMLS and LLAD algorithms in hardware. We derive error computing algorithms to comprehend the nonlinear error functions for LMLS and LLAD and map them onto hardware. We also propose a novel variable-a scheme to boost the original LMLS algorithm and prove its robustness and suitability for VLSI implementations in sensible applications. Detailed bit width and error analysis are applied for the proposed VLSI fixed point implementations. Postlayout implementation results show that with an extra multiplier over typical least mean sq. (LMS), 7-dB improvement in steady-state mean square deviation performance will be achieved and with the proposed variable-a theme, 12-dB improvement can be achieved while not compromising the convergence. We tend to can show that LMLS can doubtless replace LMS in sensible applications, by demonstrating an indication-of-concept by extending the framework to transform domain adaptive filters.