PROJECT TITLE :

Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technologyfor Low-Voltage Operation - 2016

ABSTRACT:

The previously proposed average-8T static random access memory (SRAM) features a competitive area and does not need a write-back theme. Within the case of a median-8T SRAM architecture, a full-swing native bitline (BL) that's connected to the gate of the browse buffer can be achieved with a boosted wordline (WL) voltage. However, within the case of a median-8T SRAM based on a sophisticated technology, like a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, as a result of it degrades the scan stability of the SRAM. Thus, a full-swing native BL can not be achieved, and also the gate of the browse buffer can't be driven by the full provide voltage (VDD), ensuing during a considerably large browse delay. To beat the on top of disadvantage, during this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM design, full swing of the native BL is ensured by the utilization of cross-coupled pMOSs, and the gate of the read buffer is driven by a full VDD, without the requirement for the boosted WL voltage. Varied configurations of the proposed SRAM design, that stores multiple bits, are analyzed in terms of the minimum operating voltage and space per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of zero.forty two V and a scan delay that's 62.six times lesser than that of the average-8T SRAM primarily based on the twenty two-nm FinFET technology.