PROJECT TITLE:

Design of area and power efficient digital FIR filter using modified MAC unit - 2015

ABSTRACT:

A completely unique scheme for the planning of an area and power economical digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied during this project. The key blocks of the filter are multipliers and adders, in that multiplier is that the one which occupies the main silicon area and consumes more power. In general, the multiplication operations are performed by the shift and add logic. Most of the DSP applications demand faster adders for its arithmetic computations. Carry Select Adder (CSLA) may be a well known adder for its faster computation time. Recently, an economical Carry Choose Adder (CSLA) was proposed which significantly cut back the realm and power by eliminating the redundant logic gates at every bit level. During this project, we have a tendency to propose an area and power efficient FIR filter implementation using changed Multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is estimated with the MAC unit realized by the conventional adder and therefore the changed carry select adder furthermore. The proposed FIR filter design with length of five-tap and nine-tap are developed using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC synthesis results show that the world Delay Product(ADP) of the proposed five-faucet and 9-faucet filter gains an improvement of 18.twenty sixp.c and 13.ninety fourp.c, respectively over the conventional method. Similarly, the Power Delay Product(PDP) is improved by sixteen.80p.c and twelve.54p.c, respectively.