PROJECT TITLE:

Design of area and power aware reduced Complexity Wallace Tree multiplier - 2015

ABSTRACT:

Multiplier could be a vital block in high speed Digital Signal Processing Applications. With the a lot of advance techniques in wireless communication and high-speed ULSI techniques in recent era, the a lot of stress in fashionable ULSI design below that main constraints are Power, Silicon area and delay. In all the high-speed application to Very Large Scale Integration fields, quick speed and less area is needed. There are 2 approaches to enhance the speed of multipliers specifically booth algorithm and alternative is Wallace tree algorithm. Generally, multipliers need high latency during the partial merchandise addition and standard multipliers have additional stages thus delay is additional. However, in this project, the work has been done to scale back the realm by using energy efficient CMOS Full Adder. To implement the high-speed multiplier, Wallace tree multiplier is designed and it's a 3-stage operation, that again ends up in lesser range of stages and subsequently less variety of transistors .Moreover the gate count is considerably reduced. Multipliers and their associated circuits like 0.5 adders, full adders and accumulators consume a significant portion of most high-speed applications. So, it is necessary to increase their performance with size potency by customization. In order to cut back the hardware complexity which ultimately reduces an space and power, Energy Economical full adders plays a vital role in Wallace tree multiplier. Reduced Complexity Wallace multiplier (RCWM) will have fewer adders than Standard Wallace multiplier (SWM). The Reduced complexity reduction method greatly reduces the amount of [*fr1] adders with 65-75 percent reduction in an space of half adders than normal Wallace multipliers.