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  4. Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016
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Category: MTech VLSI Projects
By MTech Projects
MTech Projects
01.Jun
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Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016

PROJECT TITLE :

Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016

ABSTRACT:

Quantum Dot Cellular Automata has attracted a heap of attention because of its extremely tiny feature size and ultra low power consumption. It may be a doable alternative for transistor based mostly technology. This paper presents the Single Layered style and construction of Logic Generator Block which generates the logic of numerous devices like one-Bit comparator, 1- Bit Half Adder, 1-Bit Half Subtractor, AND gate, XOR gate, NOR gate and XNOR gate. Proposed style is price effective and easy to fabricate thanks to absence of wire crossings. This block will be made additional economical by using control lines. Depending on individual worth on management line, logic of individual device will be generated. QCADesigner two.zero.3 tool is used for style and simulation of Logic Generator Block.

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Previous article: Design and simulation of Turbo encoder in quantum-dot cellular automata - 2016 Design and simulation of Turbo encoder in quantum-dot cellular automata - 2016 Next article: A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits - 2016 A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits - 2016
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