PROJECT TITLE :

An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016

ABSTRACT:

This paper presents the design of reversible fault tolerant architecture of logic parts of LUT (look-up table) based Field Programmable Gate Array (FPGA). The proposed logic parts are master slave Flip Flop, D-Latch and multiplexer. A replacement four×four and a new vi×six fault tolerant reversible gates are proposed for planning economical reversible fault tolerant D-latch, master slave Flip Flop and multiplexer, respectively. The look of the proposed logic parts achieve the development of forty one.sixty sevenpercent in terms of variety of gates compared to the simplest known existing approach. Besides, the proposed logic parts outperform the best existing technology by 13.33p.c and 27.twenty sevenp.c in terms of quantum price and unit delay, respectively. Finally, the efficiency of the proposed parts are clarified by implementing an n-bit adder using the proposed Configurable Logic Block (CLB) of FPGA with sixty.ninep.c power savings and twenty three.fifty six% delay minimization.