PROJECT TITLE :

Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization

ABSTRACT:

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based mostly transmitters via equation-based optimization and provides practical design pointers that can facilitate achieving optimum power potency. An accurate equation-based mostly optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific style specifications and process technologies. The proposed optimization framework will verify optimum clock edge-rate (i.e., ratio of rise/fall time to clock amount) and inter-stage voltage swings that enable important power savings while not affecting performance. Varied transmitter style tradeoffs were analyzed for 45-nm, sixty five-nm, and 90-nm technologies considering information rate, clock edge-rate, and inter-stage swing optimization. Based mostly on the analysis results, we tend to determined the foremost energy-efficient information rate that can be achieved with acceptable power overhead for every technology node. Also, we tend to identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to forty three% with inter-stage swing optimization with all different style constraints held constant.