PROJECT TITLE :

Iterative Gain Enhancement in an Algorithmic ADC

ABSTRACT:

This paper presents a fourteen.9-bit three.57-MS/s algorithmic ADC that uses iterative gain enhancement, a method that uses multiple clock phases to extend the effective op-amp gain during a switched-capacitor circuit. Using an op-amp that gives solely thirty-dB loop gain in an exceedingly feedback circuit without gain enhancement, application of the iterative gain enhancement technique boosts the loop gain to eighty one dB. The algorithmic ADC uses a capacitor sharing and scaling technique, which saves power and reduces errors. The ADC has an energetic area of zero.75 in zero.twenty five- CMOS and dissipates 16.a pair of mW. Iterative gain enhancement will increase the SNDR from forty four.half dozen dB to 78.five dB and also the SFDR from forty five.nine dB to ninety six.a pair of dB. Reducing the amount of gain-enhancement iterations for the LSBs will increase the conversion rate from three.fifty seven MS/s to 4.65 MS/s with solely minor performance degradation.