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A Traffic Load Balancing Framework for Software-Defined Radio Access Networks Powered by Hybrid Energy Sources |
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2 |
Recommender System and Web 2.0 Tools to Enhance a Blended Learning Model |
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DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors |
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How the Brain Formulates Memory: A Spatio-Temporal Model Research Frontier |
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Adaptive Cache and Concurrency Allocation on GPGPUs |
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Gender classification based on fuzzy clustering and principal component analysis |
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Parasitic-Aware Design of Integrated DC–DC Converters With Spiral Inductors |
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Green’s Function Using Schelkunoff Integrals for Horizontal Electric Dipoles Over an Imperfect Ground Plane |
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9 |
Understanding openness |
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10 |
A Hybrid Semi-Digital Transimpedance Amplifier With Noise Cancellation Technique for Nanopore-Based DNA Sequencing |
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A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory |
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12 |
Time-Aware VMFlow Placement, Routing, and Migration for Power Efficiency in Data Centers |
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13 |
Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers |
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14 |
Toward a Unified Characterization of Mapping Algorithms in Cloud and MPSoC Environments Using a Literature-Based Approach |
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RFFE: A Buffer Cache Management Algorithm for Flash-Memory-Based SSD to Improve Write Performance |
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16 |
Aging degree evaluation for paper-oil insulation using the recovery voltage method |
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17 |
Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck |
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18 |
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures |
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19 |
Properties of the Energy Transport for Plane-Parallel Polychromatic Surface Gravity Waves in Waters of Arbitrary Depth |
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20 |
Global versus essential post-disaster re-provisioning in telecom mesh networks |
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21 |
Real time identification of coherent groups for controlled islanding based on graph theory |
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22 |
Automated Engine Calibration of Hybrid Electric Vehicles |
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23 |
Bi-anisotropic Metamaterials Effective Constitutive Parameters Extraction Using Oblique Incidence S-Parameters Method |
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24 |
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding |
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25 |
Performance analysis of Bayesian coalition game-based energy-aware virtual machine migration in vehicular mobile cloud |
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26 |
Toward energy-efficient cloud computing: Prediction, consolidation, and overcommitment |
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27 |
Remained p-GaN effect to turn-off energy loss (Eoff) in p-GaN gate power devices |
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28 |
Improper Signaling for Symbol Error Rate Minimization in -User Interference Channel |
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29 |
Time-Division Multiplexing for Testing DVFS-Based SoCs |
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30 |
PHEVs Bidirectional Charging/Discharging and SoC Control for Microgrid Frequency Stabilization Using Multiple MPC |
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31 |
Reversible Color Spaces without Increased Bit Depth and Their Adaptive Selection |
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32 |
Exploring Data-Level Error Tolerance in High-Performance Solid-State Drives |
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33 |
Architecting Flash-based Solid-State Drive for High-performance I/O Virtualization |
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34 |
Soft Failures in Large Datacenters |
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35 |
An Overview of Static Pipelining |
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36 |
A Case for Hybrid Discrete-Continuous Architectures |
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37 |
Cache Impacts of Datatype Acceleration |
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38 |
A HW/SW Co-designed Programmable Functional Unit |
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39 |
Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs |
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40 |
A High-Level Power Model for MPSoC on FPGA |
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41 |
Multilevel Cache Modeling for Chip-Multiprocessor Systems |
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42 |
Heterogeneity in “Homogeneous” Warehouse-Scale Computers: A Performance Opportunity |
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43 |
On Supporting Rapid Thermal Analysis |
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44 |
Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks |
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45 |
Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor |
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46 |
Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities |
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47 |
Fault-Tolerant Vertical Link Design for Effective 3D Stacking |
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