PROJECT TITLE :

Time-Division Multiplexing for Testing DVFS-Based SoCs

ABSTRACT:

Dynamic voltage-frequency scaling (DVFS) is used in system-on-chips (SoCs) for power management, but it will increase check time as a result of every core should be tested at multiple voltage settings. In addition, testing at lower power provide voltage settings increases the length of each test thanks to the corresponding reduction in frequencies that may be used for scan shift operations. Existing check scheduling techniques don't take into account take a look at applications at multiple voltage settings, so they're not effective for reducing take a look at time for DVFS-based mostly SoCs. We tend to propose a time-division multiplexing (TDM) architecture, that uses the highest out there frequency for shifting check knowledge into the SoC and then distributes the take a look at data into multiple cores using lower shift frequencies. TDM is accompanied by 3 check scheduling methods, that are appropriate for different scenarios: 1) an integer linear programming-based mostly formulation that provides optimal results for SOCs of moderate size; 2) a greedy approach that has sensible results with terribly short run time even for terribly giant SoCs; and three) a rectangle-packing approach combined with simulated-annealing that offers a trade-off between run time and test-time reduction for all SoCs. Experimental results on two industrial SoCs highlight the effectiveness of TDM and also the associated scheduling ways.