PROJECT TITLE :

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

ABSTRACT:

An occasional-jitter, low-power LC-based mostly injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Primarily based on a pulse gating technique, the proposed FTL continuously tunes the oscillator’s free-running frequency to make sure sturdy operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the part-locking condition is solely determined by the injection path. This paper conjointly introduces an accurate theoretical giant-signal analysis for part domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the uneven nature of ILO’s lock-in range, and therefore the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in sixty five nm CMOS process with active area of $0.25;textmm^two$. The prototype ILCM generates output clock in the vary of six.seventy five–eight.twenty five GHz by multiplying the reference clock by sixty four. It achieves superior integrated jitter performance of $one hundred ninety;textfs_textrms$, whereas consuming two.twenty five mW power. This translates to an wonderful figure-of-benefit (FoM) of $-251;textdB$, that is the simplest reported high-frequency clock multiplier.