PROJECT TITLE :

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

ABSTRACT:

This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To realize low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.eight V and one V, respectively. A 2.5 b two-method time-interleaved a pair of.five GS/s multiplying digital-to-analog converter (MDAC) is followed by an eight b eight-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the advantages of each ADC topologies and permits significant power and complexity reduction. The high-speed a pair of.five b MDAC front-finish simplifies the complexity of your time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when brought up the ADC input, relaxing its specifications and design. To further reduce power, the two.5 b MDAC front-finish is SHA-less, and an over-vary calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is additionally proposed to align the MDAC and SAR references, whose misalignment would otherwise turn out integral non-linearity (INL) degradation. The ADC achieves $-$ sixty one.eight dB THD, fifty seven.1 dB SNR for a 500 MHz input, whereas for a two.35 GHz input it achieves $-$fifty four.7 dB THD, 46.8 dB SNR (fifty five.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is $<-$seventy dBc. The ADC consumes 150 mW and occupies but zero.five mm$^2$.