PROJECT TITLE :

A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery

ABSTRACT:

A nineteen-twenty seven Gbps receiver comprised of an eternal-time linear equalizer (CTLE) followed by a a pair of-tap call feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at 0.5 rate, that is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-kind oscillator is proposed to provide the sampling phases while not bulky inductors. It conjointly provides the advantages of tiny form issue and wide selection operation (nineteen-twenty seven Gbps) to compensate 20 dB channel loss at twelve.five GHz. Fabricated in a very 40 nm CMOS technology, the full receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is zero.09 mm2 only.