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1 |
Detecting Colluding Blackhole and Greyhole Attacks in Delay Tolerant Networks |
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2 |
Design of a novel energy efficient topology for maximum magnitude generator |
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3 |
Experimental Study of Numerical Optimization for 3-D Microstructuring Using DMD-Based Grayscale Lithography |
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4 |
Should the Desired Heading in Path Following of Autonomous Vehicles be the Tangent Direction of the Desired Path? |
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5 |
Hardness of Solving Relational Equations |
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CHCF: A Cloud-Based Heterogeneous Computing Framework for Large-Scale Image Retrieval |
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Diderot: a Domain-Specific Language for Portable Parallel Scientific Visualization and Image Analysis |
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8 |
Computational approaches for understanding the diagnosis and treatment of Parkinson's disease |
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9 |
Pseudomorphic Yttrium Iron Garnet Thin Films With Low Damping and Inhomogeneous Linewidth Broadening |
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10 |
Motor Conversion for Reduced Energy Consumption: Compressor Applications Use More Energy Than Applications with Newer Technologies |
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11 |
Self-commissioning of flux linkage curves of synchronous reluctance machines in quasi-standstill condition |
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12 |
High-order Taylor series approximation for efficient computation of elementary functions |
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13 |
Delay estimation and multipath resistance potential accuracy of continuous phase modulation signals |
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14 |
State-Space Predictive-P Control for Liquid Level in an Industrial Coke Fractionation Tower |
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15 |
Proposed Switching Losses Model for Integrated Point-of-Load Synchronous Buck Converters |
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16 |
Flexible Security-Constrained Optimal Power Flow |
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17 |
Connected Tools in Digital Design |
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18 |
Stuck Bits Study in DDR3 SDRAMs Using 45-MeV Proton Beam |
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19 |
Spelled sign word recognition using key frame |
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20 |
Biological investigations using a triple-cubesat |
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21 |
Event-Based Control and Scheduling Codesign: Stochastic and Robust Approaches |
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22 |
Load Balancing With EV Chargers and PV Inverters in Unbalanced Distribution Grids |
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23 |
Algorithms Scheduling with Migration Strategies for Reducing Fragmentation in Distributed Systems |
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24 |
Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator |
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25 |
Use of input necessary assignments for test generation based on merging of test cubes |
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26 |
Distributed estimation of non-linear functions of the state vector for multisensory continuous-time linear systems |
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27 |
Control of Transient Power During Unintentional Islanding of Microgrids |
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28 |
Morphable hundred-core heterogeneous architecture for energy-aware computation |
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29 |
Machine learning predictive modelling high-level synthesis design space exploration |
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30 |
Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow |
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31 |
Design and evaluation of a high throughput robust router for network-on-chip |
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32 |
Fast inversion algorithm in GF(2m) suitable for implementation with a polynomial multiply instruction on GF(2) |
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33 |
Evaluation of testability enhancement using software prototype |
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34 |
Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation |
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35 |
Multi-modal response compaction adaptive to x-density variation |
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36 |
Undetectable transition faults under broadside tests with constant primary input vectors |
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37 |
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform |
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38 |
Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays |
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39 |
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model |
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40 |
Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses |
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41 |
Design and security evaluation of balanced 1-of-n circuits |
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42 |
Refinement-based verification of elastic pipelined systems |
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43 |
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays |
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44 |
Design and evaluation of variable stages pipeline processor with low-energy techniques |
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45 |
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures |
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46 |
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles |
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47 |
Test vector chains for increased resolution and reduced storage of diagnostic tests |
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48 |
Towards power-elastic systems through concurrency management |
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49 |
Verification by parts: reusing component invariant checking results |
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50 |
Routing of asynchronous Clos networks |
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51 |
Signal transition graph decomposition: internal communication for speed independent circuit implementation |
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52 |
Long-run order-independence of vector-based transition systems |
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53 |
Efficient model checking of PSL safety properties |
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54 |
Encoding of processor instruction sets with explicit concurrency control |
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