VLSI FPGA IEEE Projects For MTech ECE Students 2026

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Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems - 2017
Fast Energy Efficient Radix-16 Sequential Multiplier - 2017
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017
High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder - 2017
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs - 2017
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction - 2017
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding - 2017
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity - 2017
Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic - 2017
Multi-operand logarithmic addition/subtraction based on Fractional Normalization - 2017
On the Implementation of Computation-in-Memory Parallel Adder - 2017
On the VLSI Energy Complexityof LDPC Decoder Circuits - 2017
Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor - 2017
Optimization of Constant Matrix Multiplication with Low Power and High Throughput - 2017
Probabilistic Error Analysis of Approximate Recursive Multipliers - 2017
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder - 2017
Realization of a hardware generator for the Sum of Absolute Difference component - 2017
Reconfigurable Constant Multiplication for FPGAs - 2017
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing - 2017
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017

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Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems - 2017

Fast Energy Efficient Radix-16 Sequential Multiplier - 2017

High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017

High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder - 2017

Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs - 2017

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction - 2017

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding - 2017

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity - 2017

Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic - 2017

Multi-operand logarithmic addition/subtraction based on Fractional Normalization - 2017

On the Implementation of Computation-in-Memory Parallel Adder - 2017

On the VLSI Energy Complexityof LDPC Decoder Circuits - 2017

Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor - 2017

Optimization of Constant Matrix Multiplication with Low Power and High Throughput - 2017

Probabilistic Error Analysis of Approximate Recursive Multipliers - 2017

RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder - 2017

Realization of a hardware generator for the Sum of Absolute Difference component - 2017

Reconfigurable Constant Multiplication for FPGAs - 2017

RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing - 2017

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017

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