PROJECT TITLE :

Variability in Multistage Synchronizers

ABSTRACT:

System-on-a-chip designs usually use multiple clock domains to interface many externally clocked circuits operating at different frequencies and to reduce power and space by breaking giant clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate between the various clock domains. To realize high reliability margins in high-frequency designs implemented in trendy process technologies, multistage synchronizers are usually used. During this paper, we have a tendency to develop analytical formulas to calculate the chance of failure and the quantity of stages to use in such synchronizers. We compare our model with those reported in previous publications and show that almost all existing models underestimate mean time between failures (MTBF). Our model calculates an MTBF lower certain with significantly smaller margins. The concept of an effective resolution time constant for multistage synchronizers is introduced and the important effects of clock duty cycle and method variability are addressed. These method variability effects will be minimized by use of easy style rules for the synchronizer. For safety-essential applications, calculation of the probability of a failure-free lifetime for all merchandise in a very production run is developed and a easy lower certain comes.