PROJECT TITLE :

Pipelined median architecture

ABSTRACT:

The core processing step of the noise reduction median filter technique is to seek out the median at intervals a window of integers. A four-step procedure technique to compute the running median of the last N W-bit stream of integers showing space and time advantages is proposed. The strategy slices integers into teams of B-bit employing a pipeline of W/B blocks. From the tactic, an architecture is developed giving a designer the flexibleness to exchange space gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in space of around 40p.c, or in frequency of operation of around 20p.c, are clearly observed by FPGA circuit implementations compared with latest strategies within the literature.