PROJECT TITLE :

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

ABSTRACT:

For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in ten-nm technology, considering capacitance thanks to metal pattering and device variability to line target scan current for various variants of SRAM design to see technology high-density (HD) SRAM cell. The VT-targeting methodology brings into play the worst case scan and write margins offered for SRAM cell to see nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the identical space of $0.0546~mu $ $mathrmm^mathrm 2$ with fifty% higher leakage, 12a pair of SRAM outperform by 5% and 20% improved browse and write margins, respectively. The twelvea pair of SRAM as HD cell reduces the value of the technology by sharing P-channel field effect transistor (PFET) and N-channel field impact transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares solely NFET VT mask. The 11one SRAM can achieve target performance at lesser area of $0.048~mu $ $mathrmm^mathrm 2$ by compromising read stability, which will lead to lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider a further $1sigma _mathrm mathbf rsnm$ margin to retain the same yield in 10-nm-technology era.