PROJECT TITLE :

General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters

ABSTRACT:

Energy loss due to prime/bottom plate parasitic capacitances is one in all the factors determining the potency of integrated switched capacitor DC/DC converters. This loss is particularly significant when MOS gate or deep trench capacitors are used. We have a tendency to propose a way for top/bottom-plate charge recycling that can be applied with low overhead independently of the converter architecture. 2 examples of application of the technique are presented. Initial, it's shown how the technique can be applied to any converter by transforming it to an interleaved implementation. This approach is demonstrated in a very series-parallel 1/3 down converter achieving a maximum load power of 240 . Simulation results show an improvement of 7% in the efficiency by decreasing the high/bottom-plate parasitic capacitance losses by fifty two%. The second example considers an design where the proposed technique can be directly applied while not additional transformations of the converter implementation. It is a hoop modular design converter, which was fabricated during a a hundred thirty nm CMOS method. An potency improvement of up to 4% was achieved in measurements by reducing the high/bottom plate losses by seventy%, therefore reaching an impressive potency of eighty.six% at a conversion ratio of 2/3 and a maximum load power of two.2 mW.