PROJECT TITLE :

A CMOS Low-Dropout Regulator With Dominant-Pole Substitution

ABSTRACT:

A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a better frequency pole substitutes in and becomes the new dominant pole. With DPS, the loop bandwidth of the proposed LDO will be significantly extended, whereas a commonplace worth and large output capacitor for transient purpose can still be used. The resultant LDO benefits from both the fast response time because of the wide loop bandwidth and the massive charge reservoir from the output capacitor to attain the many enhancement within the dynamic performances. Implemented with a industrial 0.eighteen-μm CMOS technology, the proposed LDO with DPS is validated to be capable of delivering one hundred mA at one.zero-V output from a one.a pair of-V supply, with current efficiency of 99.eighty six%. Experimental results conjointly show that the error voltage at the output undergoing one hundred mA of load transient in 10-ns edge time is regarding 25 mV. Line transient responses reveal that no more than 20-mV instantaneous changes at the output when the provision voltage swings between one.two and 1.eight V in a hundred ns. The power-offer rejection ratio at 3 MHz is -47 dB.