PROJECT TITLE :

A Vectorless Approach for Predicting Switching Activity in a Digital Circuit

ABSTRACT:

Existing vectorless methods use a statistical approach to estimate the average range of switching events in a very digital circuit. While these methods enable one to predict the common power consumption, a vital parameter for several digital styles, they can't be used to predict the statistical variation in power consumed in every clock cycle, that is important to estimate the bounds on power supply noise. A vectorless method is proposed for estimating the variance in the quantity of switching events across a digital style. This result could be used to estimate variance in power supply noise. The approach was tested on a 5 × five adder array. The quality deviation in the whole number of switching events can be found among one% for this design. Together with covariance among switching events at completely different gates was vital. When covariance was ignored, the quality deviation was underestimated by nearly eighty four%. The proposed approach allows speedy estimation of a reasonable worst case range of switching events which will occur in a single clock cycle.