PROJECT TITLE :

A New Quasi-3-D Compact Threshold Voltage Model for Pi-Gate (ΠG) MOSFETs With the Interface Trapped Charges

ABSTRACT:

With the results of equivalent oxide charges on the flat-band voltage, a new quasi-3-dimensional (quasi-3-D) compact threshold voltage model is presented for the pi-gate (ΠG) MOSFETs with the interface trapped charges primarily based on the quasi-3-D scaling equation that accounts for equivalent range of gates and virtual back gate effects induced by the normalized gate extension depth in the buried oxide. The model reveals that a thin gate oxide will effectively scale back the threshold voltage degradation caused by the trapped charges. Opposite to the thin gate oxide, a thick silicon is needed to alleviate the threshold voltage shift resulted from the negative trapped charges. For the short-channel behavior, the device with negative/positive trapped charges will decrease/increase the brink voltage roll-off caused by the short-channel effects. Because of its computational efficiency and easy formula, the model will be easily used to explore the edge behavior for the charges trapping ΠG MOSFETs.