PROJECT TITLE :

DRAMA: An Architecture for Accelerated Processing Near Memory

ABSTRACT:

Improving energy efficiency is crucial for both mobile and high-performance computing systems whereas a large fraction of total energy is consumed to transfer data between storage and processing units. Thus, reducing data transfers across the memory hierarchy of a processor (i.e., off-chip memory, on-chip caches, and register file) will greatly improve the energy potency. To this end, we have a tendency to propose an architecture, DRAMA, that 3D-stacks coarse-grain reconfigurable accelerators (CGRAs) atop off-chip DRAM devices. DRAMA does not need changes to the DRAM device architecture, other than through-silicon vias (TSVs) that connect the DRAM device's internal I/O bus to the CGRA layer. We have a tendency to demonstrate that DRAMA will scale back the energy consumption to transfer information across the memory hierarchy by 66-95 percent while achieving speedups of up to eighteen× over a commodity processor.