PROJECT TITLE :

An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications

ABSTRACT:

Many image/video processing algorithms require FIFO for filtering. The FIFO size is proportional to the length of the filters and input knowledge width, inflicting large area and power consumption. We tend to have proposed an energy- and area-economical FIFO design for image/video applications through FIFO with error-reduced knowledge compression (FERDC) and near-threshold operation. On architecture level, FERDC technique is proposed to scale back the size and power consumption of the FIFO by utilizing the spatial correlation between neighboring pixels and performing error-reduced information compression along with quantization to minimize the mean square error (MSE). On circuit level, close to-threshold operation is adopted to achieve more power reduction whereas maintaining the specified performance. To demonstrate the proposed FIFO, it's been implemented using a 0.18-μm CMOS process technology. The implementation covers completely different FIFO length, as well as 128, 256, 512, and 1024. The experimental results show that the proposed FIFO operating at 0.five V and twenty eight.57 MHz achieves up to 99%, sixty fivepercent, and thirty four.91percent reduction in dynamic power, leakage power, and area, respectively, with a little MSE of two.76, compared with the conventional FIFO design. The proposed FIFO will be applied to a wide range of image/video signal processing applications to attain high space and energy potency.