PROJECT TITLE :

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST - 2016

ABSTRACT:

Throughout at-speed check of high performance sequential ICs using scan-based mostly Logic BIST, the IC activity factor (AF) induced by the applied test vectors is considerably higher than that experienced throughout its in field operation. Consequently, power droop (PD) could happen during each shift and capture phases, which can abate the circuit underneath test (CUT) signal transitions. At capture, this phenomenon is seemingly to be erroneously recognized as because of delay faults. As a result, a false check fail may be generated, with consequent increase in yield loss. During this paper, we have a tendency to propose two approaches to scale back the PD generated at capture during at-speed take a look at of sequential circuits with scan-based mostly Logic BIST using the Launch-On-Shift scheme. Each approaches increase the correlation between adjacent bits of the scan chains with respect to standard scan-primarily based LBIST. This approach, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is additionally reduced compared to standard scan-based mostly LBIST. The former approach, hereinafter referred to as Low-Value Approach (LCA), allows a 50 p.c reduction within the worst case magnitude of PD during standard logic BIST. It needs a tiny cost in terms of space overhead (of approximately one.five p.c on average), and it does not increase the quantity of check vectors over the traditional scan-primarily based LBIST to realize the same Fault Coverage (FC). Moreover, compared to 3 recent alternative solutions, LCA options a comparable AF in the scan chains at capture, whereas requiring lower check time and area overhead. The second approach, hereinafter known as High-Reduction Approach (HRA), allows scalable PD reductions at capture of up to eighty seven %, with limited additional prices in terms of space overhead and range of needed check vectors for a given target FC, over our LCA approach. Particularly, compared to two of the 3 recent various solutions mentioned above, HRA permits a considerably lower AF in the scan chains throughout the appliance of test vectors, whereas requiring either a comparable space overhead or a considerably lower check time. Compared to the remaining alternative solutions mentioned on top of, HRA allows the same AF within the scan chains at capture (approximately 90 p.c below typical scan-based LBIST), whereas requiring a significantly lower test time (approximately four.87 times on average lower variety of take a look at vectors) and comparable area overhead (of approximately 1.9 percent on average).