ABSTRACT:

Modular arithmetic operations (inversion, multiplication and exponentiation) are utilized in many cryptography applications. RSA and elliptic curve cryptography (ECC) are two of the foremost well established and widely used public key cryptographic (PKC) algorithms. The encryption and decryption of those PKC algorithms are performed by repeated modulo multiplications. These multiplications differ from those encountered in signal processing and general computing applications in their sheer operand size. Key sizes in the range of 512~1024 bits and a hundred and sixty~512 bits are typical in RSA and ECC, respectively . Hence, the long carry propagation of enormous integer multiplication is that the bottleneck in hardware implementation of PKC. The residue number system (RNS) has emerged as a promising alternative number illustration for the design of faster and low power multipliers owing to its benefit to distribute a long integer multiplication into several shorter and freelance modulo multiplications. RNS has additionally been successfully used to style fault tolerant digital circuits.

A special moduli set of forms 2n-1, 2n, 2n +1 are preferred over the generic moduli thanks to the ease of hardware implementation of modulo arithmetic functions  in addition to system-level inter-modulo operations, like RNS-to-binary conversion and sign detections. To facilitate style of high-speed full-adder primarily based modulo arithmetic units, it's worthwhile to stay the moduli of a high-DR RNS in types of 2n-1, 2n, 2n +1.The modulo 2n-one multiplier is sometimes the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier.With this precept, a family of radix-eight Booth encoded modulo 2n-one multipliers, with delay adaptable to the RNS multiplier delay, is proposed. The modulo 2n-one multiplier delay is made scalable by controlling the word-length of the ripple carry adder, utilized for radix-8 hard multiple generation.

The initial-ever family of low-space and low-power radix-8 Booth encoded modulo 2n-one multiplier whose delay will be tuned to match the RNS delay closely has been proposed in this paper. A CSA tree with end-around-carry addition for accumulation of redundant partial merchandise and a Sklansky parallel-prefix structure has additionally been implemented.