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  4. Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes - 2018
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Category: MTech DSP Projects
By MTech Projects
MTech Projects
28.Nov
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Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes - 2018

PROJECT TITLE :

Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes - 2018

ABSTRACT:

List successive cancellation decoder (LSCD) architectures have been recently proposed for the decoding of polar codes to attain high decoding performance. However, the existing architectures for updating the partial sums of all the list candidate methods scale linearly with the code length and hence have important space and delay overhead for polar codes with long code length or list size. During this Project, an inventory high-performance partial-total network (LHPPSN) is proposed based on a folded partial-add network (PSN) design of which the complexity does not scale with the code length. A design based mostly on replicating units of high-performance PSN and lazy copying is initial presented. To boost the area and performance, a new methodology based mostly on indices copying is proposed next. Additionally, by exploiting the properties of PSN, the complexity is additional reduced by sharing the trail copying logic. Experimental results show that using the proposed LHPPSN results in a lot of than 70p.c and fortyp.c reduction in area and delay, respectively, for polar codes with massive code length or list size, in comparison with the state-of-the-art LSCD PSN architectures.

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