JA Purity IV
  • HOME
    • Business
    • Corporate
    • Logistics
    • Product
    • News / Magazine
  • MTECH PROJECTS
    • COMPUTER SCIENCE
      • MTech Python Projects
        • Machine Learning Projects
        • Deep Learning Projects
        • Blockchain Projects
        • django Projects
      • MTech Java Projects
        • Cloud Computing Projects
        • Data Mining Projects
        • Mobile Computing Projects
        • Networking Projects
      • MTech NS2 Projects
        • Wireless Communication Projects
        • Vehicular Technology Projects
      • MTech Hadoop Projects
      • MTech Android Projects
    • ELECTRONICS
      • MTech DSP Projects
      • MTech DIP Projects
      • MTech VLSI Projects
      • MTech Communication Projects
    • ELECTRICAL
      • MTech Power Systems Projects
      • MTech Power Electronics Projects
      • MTech Control Systems Projects
    • OTHER
      • Chemical Projects
      • Mechanical Projects
      • All Other Projects
  • EMBEDDED KITS
    • MTech Embedded Kits
    • BTech Embedded Kits
  • PROJECTS+
  • PUBLISHING
    • Research Publishing
    • Authors Guidelines
    • Publishing Policy
  • CONTACT US

Contact Us

  • 4517 Washington Ave. Manchester, Kentucky 39495
  • (201) 555-0124
  • hello@purityiv.com

Welcome to MTech Projects - Online Projects for MTech Students

  • My Account
  • Careers
  • Downloads
  • Blog
JA Purity IV
  • Email Us
  • Phone Number
  • Open Hours
  • HOME
    • Business
    • Corporate
    • Logistics
    • Product
    • News / Magazine
  • MTECH PROJECTS

    MTech Python Projects

    • Machine Learning Projects
    • Deep Learning Projects
    • Blockchain Projects
    • django Projects

    MTECH JAVA PROJECTS

    • Cloud Computing Projects
    • Data Mining Projects
    • Mobile Computing Projects
    • Networking Projects

    MTECH NS2 PROJECTS

    • Wireless Communication Projects
    • Vehicular Technology Projects
    • MTech Hadoop Projects
    • MTech Android Projects

    ELECTRONICS

    • MTech DSP Projects
    • MTech DIP Projects
    • MTech VLSI Projects
    • MTech Communication Projects

    ELECTRICAL

    • MTech Power Systems Projects
    • MTech Power Electronics Projects
    • MTech Control Systems Projects

    OTHER

    • Chemical Projects
    • Mechanical Projects
    • All Other Projects
  • EMBEDDED KITS
    • MTech Embedded Kits
    • BTech Embedded Kits
  • PROJECTS+
  • PUBLISHING
    • Research Publishing
    • Authors Guidelines
    • Publishing Policy
  • CONTACT US

Project Enquiry

  1. You are here:  
  2. Home
  3. MTech DSP Projects
  4. A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size - 2018
Details
Category: MTech DSP Projects
By MTech Projects
MTech Projects
28.Nov
Hits: 1

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size - 2018

PROJECT TITLE :

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size - 2018

ABSTRACT:

As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted a lot of analysis interest recently. Compared with other standard FEC codes, polar codes decoded by list successive cancellation decoding (LSCD) with a giant list size have higher error correction performance. But, because of the serial decoding nature of LSCD and therefore the high complexity of list management (LM), the decoding latency is high, which limits the usage of polar codes in sensible applications that need low latency and high throughput. In this work, we study the high-throughput implementation of LSCD with a giant list size. Specifically, at the algorithmic level, to attain an occasional decoding latency with moderate hardware complexity, 2 decoding schemes, a multi-bit double thresholding theme and a partial G-node look-ahead scheme, are proposed. Then, a high-throughput VLSI design implementing the proposed algorithms is developed with optimizations on totally different computation modules. From the implementation results on UMC ninety nm CMOS technology, the proposed design achieves decoding throughputs of one.103 Gbps, 97seven Mbps and 827 Mbps when the list sizes are eight, 16 and 32, respectively.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

Previous article: A Fast Converging Channel Estimation Algorithm for Wireless Sensor Networks - 2018 A Fast Converging Channel Estimation Algorithm for Wireless Sensor Networks - 2018 Next article: A Lattice Basis Reduction Approach for the Design of Finite Wordlength FIR Filters - 2018 A Lattice Basis Reduction Approach for the Design of Finite Wordlength FIR Filters - 2018
COMPUTER SCIENCE PROJECTS ELECTRONICS PROJECTS MTech DSP Projects MTech DIP Projects MTech VLSI Projects MTech VHDL Projects MTech Verilog Projects MTech Communication Projects ELECTRICAL PROJECTS EMBEDDED PROJECTS MECHANICAL PROJECTS

sell academic m.tech, btech and be projects online

sell academic m.tech, btech and be projects online

Academic Final Year Projects

QUICK LINKS

  • Python Projects
  • Java Projects
  • Android Projects
  • Digital Signal Processing
  • Image Processing Projects
  • VLSI Projects
  • Power Systems
  • Power Electronics
SUPPORT
+91 9573777164
9:00am - 6:00pm IST
info@mtechprojects.com

Navigate

  • ABOUT
  • TESTIMONIALS
  • FIND A DEALER
  • CAREERS

CONTACT

  • CONTACT
  • FAQ
  • RESOURCES
  • EMAIL US

Useful links

  • REFUND & RETURN POLICY
  • PRIVACY POLICIES

Support

  • FACEBOOK
  • TWITTER
  • PINTEREST
  • GOOGLE PLUS
Copyright © 2026 MTech Projects. All Rights Reserved.