PROJECT TITLE :

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

ABSTRACT:

This work proposes a unique methodology to guage SRAM-based FPGA’s susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU check with serious-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to watch the TID-induced imprint effect inside the BlockRAM cells, a second SEU take a look at with neutrons was performed with Americium/Beryllium ( ). The noise was injected into the ability supply bus in line with the IEC sixty one.00zero-four-twenty nine commonplace and consisted of voltage dips with sixteen.67p.c and 25% of the FPGA’s VDD at frequencies of ten Hz and five kHz, respectively. At the top of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA’s BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.