PROJECT TITLE :

An Optimized Resistance Characterization Technique for the Next Generation Magnetic Random Access Memory

ABSTRACT:

This paper presents an accurate resistance characterization technique for magnetic random access memory (MRAM), like STT-MRAM. By annulling the mismatch effect of CMOS transistors, this technique produces a resistance distribution profile of MRAM devices in a giant array that reflects the actual device statistics. A one Kb array of MTJs with an intrinsic threeσ low resistance state distribution modeled with Verilog-A provides the reference device statistics. Monte Carlo simulation results of common array configurations show the strategy's generic benefits of tightened distributions of the mean resistance price and customary deviation (SD) of the characterized one Kb devices than the reference methodology. Technology scaling study shows the sustainability of the proposed methodology with an improvement of the SD of the mean resistance distribution by at least thirty seven.6%. The mean and SD of the quality deviation distribution were improved by at least 25.one% and sixty seven.two% as compared to the reference methodology, respectively.